Improved active device isolation techniques may be desirable in order to facilitate ongoing attempts to increase integration density in integrated circuit devices by designing devices having reduced unit cell size. Conventional device isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) techniques, for example. Such device isolation techniques are disclosed in U.S. Pat. Nos. 6,187,651, 6,218,273, 6,251,746, 5,885,883, 5,940,716, 6,001,696 and 6,037,237.
Such techniques may, however, exhibit problems that may affect the reliability of the integrated circuit. For example, the LOCOS technique, when applied to highly integrated devices, may exhibit oxide thinning and punch through parasitics. Moreover, LOCOS techniques tend to produce devices having narrow width effect. In other words, as width of the channel of an integrated circuit is reduced, the threshold voltage of the channel may increase.
By way of further example, STI techniques that include the formation of trench isolation regions, also may exhibit problems that may affect the reliability of the integrated circuit. First, a parasitic “hump” phenomenon may occur. The hump phenomenon means that the turn-on characteristics of a transistor formed in the active region may be deteriorated because of the presence of a parasitic transistor (adjacent the sidewall portions of the active region) having a relatively low threshold voltage. Second, an inverse narrow-width effect is generated. The inverse narrow-width effect is also a parasitic phenomenon, which can, for example, lower the effective threshold voltage as the width of a gate electrode becomes narrower by a strong electric field generated at the sharp edge of the active region. Third, a gate oxide-thinning phenomenon may be generated whereby the gate oxide film formed at the sharp edge portion of the active region is thinner than the gate oxide film formed in another portion removed from the edge portion. This thinner gate oxide film may increase the likelihood of dielectric breakdown, which can deteriorate the characteristics of devices formed in the active region.
Now referring to FIG. 1, a pair of arrows denote an influence of an electric field upon an active region 13 of a specific cell in a conventional Dynamic Random Access Memory (DRAM) device having gate lines 11. FIG. 2 illustrates the effect of cell spacing (LSP) on the influence of an electric field in a conventional device. As illustrated, the narrower the cell-to-cell spacing, the greater the influence of the electric field. For example, when a voltage VNS applied to a storage node of an adjacent cell is changed from 0V to 2V, a gate voltage VG is 0.5V, and the spacing LSP is 0.1 μm, the potential scarcely changes at each position of a conventional channel. On the other hand, if the spacing LSP is 0.06 μm, the potential difference may be 0.1V or higher.
To address the issue with respect to the influence of the electric field, insulating layers, for example insulating layer 20 illustrated in FIG. 3, may be filled with a conductive material such as polysilicon 31 to shield the electric field. This technique is discussed in detail in U.S. Pat. No. 6,133,116 to Kim et al. entitled Methods of Forming Trench Isolation Regions Having Conductive Shields Therein, the disclosure of which is hereby incorporated herein by reference in its entirety. Although this approach may improve the existing techniques, it may not completely prevent other causes from lowering the threshold voltage of the device.
Recently, another approach has been suggested, in which impurities may be implanted into a device isolation layer. However, if the implanted impurities are enough to prevent the inverse narrow width effect, a junction profile of a cell may become stiff thus reducing the junction width of the cell, which is also undesirable because an electric field may get concentrated at the junction which may increase a junction leakage current.